Transistor and IC packages

Terminology
In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the tiny 'die' (integrated circuit copatibal) semiconducting material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "Semiconductor package", supports the electrical contacts which connect the device to a circuit board.

Overview
In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the tiny block of semiconducting material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

In the integrated circuit industry, the process is often referred to as packaging. Other names include semiconductor device assembly, assembly, encapsulation or sealing.

The packaging stage is followed by testing of the integrated circuit.

The term is sometimes confused with electronic packaging, which is the mounting and interconnecting of integrated circuits (and other components) onto printed-circuit boards.

A metal can with epoxy inside sits over the IC that is on a epoxy pad. The legs are metal and attach to the IC with thin gold wires. Some were fully encased in epoxy or in a metal can filled with argon, sand or epoxy. The case is often made of epoxy or plastic, and offers compact size and durability at a very low cost.

General history
The earliest integrated circuits were packaged in ceramic flat packs, which the military used for many years for their reliability and small size. Commercial circuit packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in plastic. In the 1980s VLSI pin counts exceeded the practical limit for DIP packaging, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages. Surface mount packaging appeared in the early 1980s and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-outline integrated circuit — a carrier which occupies an area about 30 – 50% less than an equivalent DIP, with a typical thickness that is 70% less.

The next big innovation was the area array package, which places the interconnection terminals throughout the surface area of the package, providing a greater number of connections than previous package types where only the outer perimeter is used. The first area array package was a ceramic pin grid array package.Not long after, the plastic ball grid array (BGA), another type of area array package, became one of the most commonly used packaging techniques.

In the late 1990s, plastic quad flat pack (PQFP) and thin small-outline packages (TSOP) replaced PGA packages as the most common for high pin count devices, though PGA packages are still often used for microprocessors. However, industry leaders Intel and AMD transitioned in the 2000s from PGA packages to land grid array (LGA) packages.

Ball grid array (BGA) packages have existed since the 1970s, but evolved into Flip-chip ball grid array packages (FCBGA) in the 1990s. FCBGA packages allow for much higher pin count than any existing package types. In an FCBGA package, the die is mounted upside-down (flipped) and connects to the package balls via a substrate that is similar to a printed-circuit board rather than by wires. FCBGA packages allow an array of input-output signals (called Area-I/O) to be distributed over the entire die rather than being confined to the die periphery.

Traces out of the die, through the package, and into the printed circuit board have very different electrical properties, compared to on-chip signals. They require special design techniques and need much more electric power than signals confined to the chip itself.

Recent developments consist of stacking multiple dies in single package called SiP, for System In Package, or three-dimensional integrated circuit. Combining multiple dies on a small substrate, often ceramic, is called an MCM, or Multi-Chip Module. The boundary between a big MCM and a small printed circuit board is sometimes blurry.

Early USSR made integrated circuit. The tiny block of semiconducting material (the "die"), is enclosed inside the round, metallic case (the "package").

Flat-packs
The original flatpack was invented by Y. Tao in 1962 while working for Texas Instruments to achieve improved heat dissipation. The dual in-line package would be invented two years later. The first devices measured 1/4 inch by 1/8 inch (3.2 mm x 6.4 mm) and had 10 leads.

The flat package was smaller and lighter than the round TO-5 style transistor packages previously used for integrated circuits. Round packages were limited to 10 leads. Integrated circuits needed more leads to take full advantage of increasing device density. Since flat packages were made of glass, ceramic and metal, they could provide hermetic seals for circuits, protecting them from moisture and corrosion. Flat packs remained popular for military and aerospace applications long after plastic packages became the standard for other application fields.

Dual in-line package
In microelectronics, a dual in-line package (DIP or DIL), or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits.

Increasingly complex circuits required more signal and power supply leads (as observed in Rent's rule); eventually microprocessors and similar complex devices required more leads than could be put on a DIP package, leading to development of higher-density packages. Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages.

A DIP is usually referred to as a DIPn, where n is the total number of pins. For example, a microcircuit package with two rows of seven vertical leads would be a DIP14. The photograph at the upper right shows three DIP14 ICs. Common packages have as few as four and as many as 64 leads. Many analog and digital integrated circuit types are available in DIP packages, as are arrays of transistors, switches, light emitting diodes, and resistors. DIP plugs for ribbon cables can be used with standard IC sockets.

DIP packages are usually made from an opaque molded epoxy plastic pressed around a tin-, silver-, or gold-plated lead frame that supports the device die and provides connection pins. Some types of IC are made in ceramic DIP packages, where high temperature or high reliability is required, or where the device has an optical window to the interior of the package. Most DIP packages are secured to a printed circuit board by inserting the pins through holes in the board and soldering them in place. Where replacement of the parts is necessary, such as in test fixtures or where programmable devices must be removed for changes, a DIP socket is used. Some sockets include a zero insertion force mechanism.

Variations of the DIP package include those with only a single row of pins, possibly including a heat sink tab in place of the second row of pins, and types with four rows of pins, two rows, staggered, on each side of the package. DIP packages have been mostly displaced by surface-mount package types, which avoid the expense of drilling holes in a printed circuit board and which allow higher density of interconnections.

Variants
Several DIP variants for ICs exist, mostly distinguished by packaging material:
 * Ceramic Dual In-line Package (CERDIP or CDIP)
 * Plastic Dual In-line Package (PDIP)
 * Shrink Plastic Dual In-line Package (SPDIP)- A denser version of the PDIP with a 0.07 in. (1.778 mm) lead pitch.
 * Skinny Dual In-line Package (SDIP or SPDIP)-Sometimes used to refer to a "narrow" 0.300 in. (or 300 thousandth of an inch) wide DIP, normally when clarification is needed e.g. for DIP with 24 pins or more, which usually come in "wide" 0.600 in. wide DIP package. An example of a typical proper full spec for a "narrow" DIP package would be 300 mil body width, 0.1" pin pitch.

EPROMs were sold in ceramic DIPs manufactured with a circular window of clear quartz over the chip die to allow the part to be erased by ultraviolet light. Often, the same chips were also sold in less expensive windowless PDIP or CERDIP packages as EPROM one-time programmable (OTP) versions. Windowed and windowless packages were also used for microcontrollers, and other devices, containing EPROM memory. Windowed CERDIP-packaged EPROMs were used for the BIOS ROM of many early IBM PC clones with an adhesive label covering the window to prevent inadvertent erasure through exposure to ambient light.

Molded plastic DIPs are much lower in cost than ceramic packages; one 1979 study showed that a plastic 14 pin DIP cost around US 63 cents, and a ceramic package cost 82 cents.

Single in-line package
Package sample for single in-line (SIL) devices A single in-line (pin) package (SIP or SIPP) has one row of connecting pins. It is not as popular as the DIP, but has been used for packaging RAM chips and multiple resistors with a common pin. SIPs group RAM chips together on a small board either by the DIP process or surface mounting SMD process. The board itself has a single row of pin-leads that resembles a comb extending from its bottom edge, which plug into a special socket on a system or system-expansion board. SIPs are commonly found in memory modules. As compared to DIPs with a typical maximum I/O count of 64, SIPs have a typical maximum I/O count of 24 with lower package costs.

One variant of the single in-line package uses part of the lead frame for a heat sink tab. This multi-leaded power package is useful for such applications as audio power amplifiers, for example.

Quad in-line package
Rockwell used a quad in-line package with 42 leads formed into staggered rows for their PPS-4 microprocessor family introduced in 1973, and other microprocessors and microcontrollers, some with higher lead counts, through the early 1990s.

The QIP, sometimes called a QIL package, has the same dimensions as a DIL package, but the leads on each side are bent into an alternating zigzag configuration so as to fit 4 lines of solder pads (instead of 2 with a DIL). The QIL design increased the spacing between solder pads without increasing package size, for two reasons:

First it allowed more reliable soldering. This may seem odd today, given the far closer solder pad spacing in use now, but in the 1970s, the heyday of the QIL, bridging of neighbouring solder pads on DIL chips was an issue at times, QIL also increased the possibility of running a copper track between 2 solder pads. This was very handy on the then standard single sided single layer PCBs. Some QIL packaged ICs had added heatsinking tabs, such as the HA1306.

Intel and 3M developed the ceramic leadless quad in-line package (QUIP), introduced in 1979, to boost microprocessor density and economy. The ceramic leadless QUIP is not designed for surface-mount use, and requires a socket. It was used by Intel for the iAPX 432 microprocessor chip set, and by Zilog for the Z8-02 external-ROM prototyping version of the Z8 microcontroller.

Code numbers, corporate production standards, patents and quality control levels
Just like vacuum tubes (valves), semiconductor packages standards may be defined by national or international industry associations such as JEDEC, Pro-Electron, or EIAJ, or may be proprietary to a single manufacturer.

Also see

 * 1) TO-18 transistor packing unit shell
 * 2) TO-92 transistor packing unit shell
 * 3) TO-3\TO-66 power transistor packing unit shell
 * 4) TO-220 power transistor packing unit shell
 * 5) Soviet КТ819ГМ NPN power transistor packing unit shell
 * 6) Single in-line (pin) package (SIP or SIPP)
 * 7) Dual in-line package (DIP or DIL)
 * 8) Integrated circuits